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a
8-Bit, High-Speed, Multiplying D/A Converter (Universal Digital Logic Interface) DAC08
full-scale currents eliminates the need for full-scale trimming in most applications. Direct interface to all popular logic families with full noise immunity is provided by the high swing, adjustable threshold logic input. High voltage compliance complementary current outputs are provided, increasing versatility and enabling differential operation to effectively double the peak-to-peak output swing. In many applications, the outputs can be directly converted to voltage without the need for an external op amp. All DAC08 series models guarantee full 8-bit monotonicity, and nonlinearities as tight as 0.1% over the entire operating temperature range are available. Device performance is essentially unchanged over the 4.5 V to 18 V power supply range, with 33 mW power consumption attainable at 5 V supplies. The compact size and low power consumption make the DAC08 attractive for portable and military/aerospace applications; devices processed to MIL-STD-883, Level B are available. DAC08 applications include 8-bit, 1 s A/D converters, servo motor and pen drivers, waveform generators, audio encoders and attenuators, analog meter drivers, programmable power supplies, CRT display drivers, high-speed modems and other applications where low cost, high speed and complete input/ output versatility are required.
FEATURES Fast Settling Output Current: 85 ns Full-Scale Current Prematched to 1 LSB Direct Interface to TTL, CMOS, ECL, HTL, PMOS Nonlinearity to 0.1% Maximum over Temperature Range High Output Impedance and Compliance: -10 V to +18 V Complementary Current Outputs Wide Range Multiplying Capability: 1 MHz Bandwidth Low FS Current Drift: 10 ppm/ C Wide Power Supply Range: 4.5 V to 18 V Low Power Consumption: 33 mW @ 5 V Low Cost Available in Die Form
GENERAL DESCRIPTION
The DAC08 series of 8-bit monolithic digital-to-analog converters provide very high-speed performance coupled with low cost and outstanding applications flexibility. Advanced circuit design achieves 85 ns settling times with very low "glitch" energy and at low power consumption. Monotonic multiplying performance is attained over a wide 20-to-1 reference current range. Matching to within 1 LSB between reference and
FUNCTIONAL BLOCK DIAGRAM
V+ 13 VLC 1 MSB B1 5 B2 6 B3 7 B4 8 B5 9 B6 10 B7 11 LSB B8 12
DAC08
BIAS NETWORK CURRENT SWITCHES 4 2 IOUT
VREF (+)
14
IOUT
VREF (-)
15 REFERENCE AMPLIFIER 16 COMP V- 3
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
DAC08-SPECIFICATIONS
(@ VS = 15 V, IREF = 2.0 mA, -55 C TA +125 C for DAC08/08A, 0 C TA for DAC08E and DAC08H, -40 C to +85 C for DAC08C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT .)
Parameter Resolution Monotonicity Nonlinearity Settling Time Symbol Conditions Min 8 8 NL tS To 1/2 LSB, All Bits Switched ON or OFF, TA = 25C1 TA = 25C1 85 0.1 135 DAC08A/H Typ Max Min 8 8 85 0.19 150 DAC08E Typ Max Min 8 8 85 0.39 150 DAC08C Typ Max
ELECTRICAL CHARACTERISTICS
+70 C
Unit Bits Bits % FS ns
Propagation Delay Each Bit All Bits Switched Full-Scale Tempco1 Output Voltage Compliance (True Compliance) Full Range Current
tPLH tPHL TCIFS
35 35 10
60 60 50
35 35 10
DAC08E VOC Full-Scale Current Change <1/2 LSB, ROUT > 20 M typ VREF = 10.000 V R14, R15 = 5.000 k TA = 25C IFR4 - IFR2 R14, R15 = 5.000 k VREF = +15.0 V, V- = -10 V VREF = +25.0 V, V- = -12 V IREF = 2 mA VLC = 0 V 2 VLC = 0 V VIN = -10 V to +0.8 V VIN = 2.0 V to 18 V V- = -15 V VS = 15 V1 -2 0.002 -10 -10 -10 10 +18 +13.5 -3
60 60 80 50
35 35 10
60 60 80
ns ns ppm/C
-10 1.984 1.992
+18 2.000
-10 1.94 1.99
+18 2.04
-10 1.94 1.99
+18 2.04
V mA
IFR4
Full Range Symmetry Zero-Scale Current Output Current Range
IFRS IZS IOR1 IOR2
0.5 0.1 2.1
4 1 2.1
1 0.2
8 2 2.1
2 0.2
16 4
A A mA
4.2 25 0.8
4.2 25 0.8 2 -2 0.002 -10 -10 -1 8 -10 10 +18 +13.5 -3
4.2 25 0.8 2 -2 0.002 -10 -10 4 -1 8 -10 10 +18 +13.5 -3
mA nA V V A A V V A mA/s
Output Current Noise Logic Input Levels Logic "0" Logic Input "1" Logic Input Current Logic "0" Logic Input "1" Logic Input Swing Logic Threshold Range Reference Bias Current Reference Input Slew Rate Power Supply Sensitivity
VIL VIL IIL IIH VIS VTHR I15 dI/dt
PSSIFS+ PSSIFS- I+ I- I+ I- I+ I- PD
-1 REQ = 200 4 8 4 RL = 100 CC = 0 pF See Fast Pulsed Ref. Info Following.1 V+ = 4.5 V to 18 V 0.0003 0.01 V- = -4.5 V to -18 V 0.002 0.01 IREF = 1.0 mA VS = 5 V, IREF = 1.0 mA VS = +5 V, -15 V, IREF = 2.0 mA VS = 15 V, IREF = 2.0 mA 5 V, IREF = 1.0 mA +5 V, -15 V, IREF = 2.0 mA 15 V, IREF = 2.0 mA 2.3 -4.3 2.4 -6.4 2.5 -6.5 33 108 135 3.8 -5.8 3.8 -7.8 3.8 -7.8 48 136 174
0.0003 0.01 0.002 0.01 2.3 -4.3 2.4 -6.4 2.5 -6.5 33 103 135 3.8 -5.8 3.8 -7.8 3.8 -7.8 48 136 174
0.0003 0.01 0.002 0.01 2.3 -4.3 2.4 -6.4 2.5 -6.5 33 108 135 3.8 -5.8 3.8 -7.8 3.8 -7.8 48 136 174
%IO/%V+ %IO/%V- mA mA mA mA mA mA mW mW mW
Power Supply Current
Power Dissipation
NOTES 1 Guaranteed by design. Specifications subject to change without notice.
-2-
REV. B
DAC08 TYPICAL ELECTRICAL CHARACTERISTICS
Parameter Reference Input Slew Rate Propagation Delay Settling Time Symbol dI/dt tPLH, tPHL tS
(@ VS = 15 V, and IREF = 2.0 mA, unless otherwise noted. Output characteristics apply to both IOUT and IOUT .)
All Grades Typical 8 35 85 Unit mA/s ns ns
Conditions TA = 25C, Any Bit To 1/2 LSB, All Bits Switched ON or OFF, TA = 25C
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Operating Temperature DAC08AQ, Q . . . . . . . . . . . . . . . . . . . . . -55C to +125C DAC08HQ, EQ, CQ, HP, EP . . . . . . . . . . . . 0C to +70C DAC08CP, CS . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature (TJ) . . . . . . . . . . . . . -65C to +150C Storage Temperature Q Package . . . . . . . . . -65C to +150C Storage Temperature P Package . . . . . . . . . -65C to +125C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300C V+ Supply to V- Supply . . . . . . . . . . . . . . . . . . . . . . . . . 36 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . V- to V- plus 36 V VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ Analog Current Outputs (at VS- = 15 V) . . . . . . . . . . 4.25 mA Reference Input (V14 to V15) . . . . . . . . . . . . . . . . . . . V- to V+ Reference Input Differential Voltage (V14 to V15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Reference Input Current (I14) . . . . . . . . . . . . . . . . . . . 5.0 mA
Package Type 16-Lead Cerdip (Q) 16-Lead Plastic DIP (P) 20-Terminal LCC (RC) 16-Lead SO (S)
JA
2
JC
Unit C/W C/W C/W C/W
100 82 76 111
16 39 36 35
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 JA is specified for worst-case mounting conditions, i.e., JA is specified for device in socket for cerdip, Plastic DIP, and LCC packages; JA is specified for device soldered to printed circuit board for SO package.
ORDERING GUIDE1
Model
DAC08AQ DAC08AQ2/883C DAC08HP DAC08HQ DAC08Q DAC08Q2/883C DAC08RC/883C DAC08EP DAC08EQ DAC08ES DAC08ES-REEL DAC08CP DAC08CQ DAC08CS DAC08CS-REEL DAC08NBC DAC08GBC DAC08GRBC
NL
0.10% 0.10% 0.10% 0.10% 0.19% 0.19% 0.19% 0.19% 0.19% 0.19% 0.19% 0.39% 0.39% 0.39% 0.39% 0.10% 0.19% 0.39%
Temperature Range
-55C to +125C -55C to +125C 0C to 70C 0C to 70C -55C to +125C -55C to +125C -55C to +125C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to +85C 0C to 70C -40C to +85C -40C to +85C 25C 25C 25C
Package Description
Cerdip-16 Cerdip-16 P-DIP-16 Cerdip-16 Cerdip-16 Cerdip-16 LCC-20 P-DIP-16 Cerdip-16 SO-16 SO-16 P-DIP-16 Cerdip-16 SO-16 SO-16 DICE DICE DICE
Package Option
Q-16 Q-16 N-16 Q-16 Q-16 Q-16 E-20 N-16 Q-16 R-16A (Narrow Body) R-16A (Narrow Body) N-16 Q-16 R-16A (Narrow Body) R-16A (Narrow Body)
# Parts Per Container
25 25 25 25 25 25 55 25 25 47 2500 25 25 47 2500
NOTES 1 Devices processed in total compliance to MIL-STD-883. Consult factory for 883 data sheet. 2 For availability and burn-in information on SO and PLCC packages, contact your local sales office. The DAC08 contains 84 transistors. Die size 63 mil x 87 mil = 5,481 square mils.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC08 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
DAC08
PIN CONNECTIONS 16-Lead Dual-In-Line Package (Q and P Suffix)
VLC 1 IOUT V-
2 3 16 COMPENSATION 15 VREF (-) 14 VREF (+) 13 V+ 12 B8 LSB 11 B7 10 B6 9
16-Lead SO (S Suffix)
V+ 1 VREF (+) VREF (-)
2 3 16 B8 LSB 15 B7 14 B6 13 B5 12 B4 11 B3 10 B2 9
DAC08RC/883 20-Lead LCC (RC Suffix)
VREF (-)
18 17 16 15 14 9 10 11 12 13
IOUT VLC
3 2
1
IOUT 4 MSB B1 5 B2 6 B3 7 B4 8
COMP 4 VLC 5 IOUT 6 V- 7 IOUT 8
NC COMP
20 19
V- 4 IOUT NC MSB B1 B2
5 6 7 8
VREF (+) V+ NC B8 LSB B7
B5
B1 MSB
NC
B3
B4
B5
NC = NO CONNECT
DICE CHARACTERISTICS
(125C Tested Dice Available)
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. V LC IOUT V- IOUT BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 (LSB) V+ V REF (+) V REF (-) COMP
DIE SIZE 0.087 0.063 inch, 5,270 sq. mils (2.209 1.60 mm, 3.54 sq. mm)
-4-
B6
REV. B
DAC08 WAFER TEST LIMITS
Parameter Resolution Monotonicity Nonlinearity Output Voltage Compliance Full-Scale Current Full-Scale Symmetry Zero-Scale Current Output Current Range
(@ VS = 15 V, IREF = 2.0 mA; TA = 25 C, unless otherwise noted. Output characteristics apply to both IOUT and IOUT .)
Symbol Conditions DAC08N Limit 8 8 0.1 +18 -10 2.04 1.94 8 2 2.1 4.2 0.8 2 VLC = 0 V VIN = -10 V to +0.8 V VIN = +2.0 V to +18 V V- = -15 V 10 10 +18 -10 -3 0.01 DAC08G Limit 8 8 0.19 +18 -10 2.04 1.94 8 4 2.1 4.2 0.8 2 10 10 +18 -10 -3 0.01 DAC08GR Limit 8 8 0.39 +18 -10 2.04 1.94 16 4 2.1 4.2 0.8 2 10 10 +18 -10 -3 0.01 Unit Bits min Bits min % FS max V max V min mA max mA min A max A max mA min mA min V max V min A max A max V max V min A max % FS/% V max
NL VOC IFS4 or IFS2 IFSS IZS IFS1 or
Full-Scale Current Change < 1/2 LSB VREF = 10.000 V R14, R15 = 5.000 k
IFS2 Logic Input "0" Logic Input "1" Logic Input Current Logic "0" Logic "1" Logic Input Swing Reference Bias Current Power Supply Sensitivity Power Supply Current Power Dissipation VIL VIH IIL IIH VIS I15 PSSIFS+ PSSIFS- I+ PD
V- = -10 V, VREF = +15 V V- = -12 V, VREF = +25 V R14, R15 = 5.000 k
V+ = +4.5 V to +18 V V- = -4.5 V to -18 V IREF = 1.0 mA VS = 15 V IREF 2.0 mA VS = 15 V IREF 2.0 mA
3.8 -7.8 174
3.8 -7.8 174
3.8 -7.8 174
mA max A max mW max
NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
-5-
DAC08
+VREF RREF OPTIONAL RESISTOR FOR OFFSET INPUTS REQ 200 0V TYPICAL VALUES: RIN = 5k +VIN = 10V RP 14 4
0mA IOUT
RIN
RL
1.0mA
15
16
2
RL
2.0mA
IOUT
NO CAP
(0000|0000) IREF = 2mA (1111|1111)
Figure 1. Pulsed Reference Operation
C2 +18V R1 = 9k C1 = 0.001 F C2, C3 = 0.01 F
Figure 4. True and Complementary Output Operation
C1
R1 2.4V 16 15 14 13 12 11 10 9 0.4V 0V 8A 0
5mV
2V
DAC08
1 2 3 4 5 6 7 8
100mV C3 -18V MIN 50ns/DIVISION
50ns
Figure 2. Burn-in Circuit
Figure 5. LSB Switching
ALL BITS SWITCHED ON
1V 2.5V
2.4V LOGIC INPUT 0.4V
1V
0.5V -0.5mA IOUT -2.5mA 100mV REQ 200 RL = 100 CC = 0 200ns/DIVISION 200ns
OUTPUT -1/2LSB SETTLING 0V +1/2LSB
10mV SETTLING TIME FIXTURE IFS = 2mA, RL = 1k 1/2LSB = 4 A
50ns 50ns/DIVISION
Figure 3. Fast Pulsed Reference Operation
Figure 6. Full-Scale Settling Time
-6-
REV. B
Typical Performance Characteristics-DAC08
5.0 TA = T MIN TO TMAX ALL BITS "HIGH" LIMIT FOR V- = -15V
PROPAGATION DELAY - ns
500
10
IFS, OUTPUT CURRENT - mA
RELATIVE OUTPUT - dB
4.0
400
R14 = R15 = 1k 8 RL 500 ALL BITS "ON" 6 VR15 = 0V 4 2 2
3.0
300
0 -2 1 -6 1. C = 15pF, V = 2.0V p-p C IN CENTERED AT +1.0V -8 LARGE SIGNAL -10 2. C = 15pF, V = 50mV p-p C IN CENTERED AT +200mV -12 SMALL SIGNAL -14 0.1 0.2 0.5 1.0 2.0 FREQUENCY - MHz -4
2.0 LIMIT FOR V- = -5V
200
1LSB = 7.8 A
1.0
100 1LSB = 61nA
0.0 0.0
1.0 2.0 3.0 4.0 IREF , REFERENCE CURRENT - mA
5.0
0
10 0.05 0.02 0.1 0.5 2.0 0.01 0.05 0.2 1.0 5.0 IFS, OUTPUT FULL SCALE CURRENT - mA
5.0
10
TPC 1. Full-Scale Current vs. Reference Current
TPC 2. LSB Propagation Delay vs. IFS
TPC 3. Reference Input Frequency Response
4.0 3.6
TA = T MIN TO TMAX
10.0
ALL BITS ON
2.0
OUTPUT CURRENT - mA
3.2 2.8 2.4
A
NOTE: POSITIVE COMMON-MODE RANGE IS ALWAYS (V+) -1.5V
8.0
1.6
LOGIC INPUT -
6.0
VTH - VLC - V
V- = -15V 2.0 1.6 1.2 0.8 0.4
V- = -5V
V+ = +15V IREF = 2mA IREF = 1mA
1.2
4.0
0.8
2.0
IREF = 0.2mA
0.4
0.0 18 -2 2 6 10 14 -14 -10 -6 V15, REFERENCE COMMON-MODE VOLTAGE - V
0 0 4.0 8.0 12.0 16.0 -12.0 -8.0 -4.0 LOGIC INPUT VOLTAGE - V
0
-50
0 50 100 TEMPERATURE - C
150
TPC 4. Reference Amp CommonMode Range
TPC 5. Logic Input Current vs. Input Voltage
TPC 6. VTH - VLC vs. Temperature
4.0 3.6
TA = T MIN TO TMAX
28 ALL BITS ON 24
OUTPUT CURRENT - mA
1.8 1.6 1.4 1.2 1.0 IREF = 2.0mA 0.8 0.6 0.4 0.2 V- = -5V V- = -15V -8 -4 0 4 8 12 16 B4 B2 B3 B5 B1
OUTPUT CURRENT - mA
3.2
OUTPUT VOLTAGE - V
20 16 12 8 4 0 4 IREF = 0.2mA -6 -2 2 6 10 OUTPUT VOLTAGE - V 14 18 8 12 -50 0 50 100 TEMPERATURE - C 150 FOR OTHER V- OR IREF. SEE OUTPUT CURRENT VS. OUTPUT VOLTAGE CURVE. SHADED AREA INDICATES PERMISSIBLE OUTPUT VOLTAGE RANGE FOR V- = -15V. I REF 2.0mA.
2.8 2.4 V- = -15V 2.0 1.6 1.2 0.8 0.4 0.0 -14 -10 IREF = 1mA V- = -5V IREF = 2mA
0 -12
LOGIC INPUT VOLTAGE - V
NOTE: B1 THROUGH B8 HAVE IDENTICAL TRANSFER CHARACTERISTICS. BITS ARE FULLY SWITCHED WITH LESS THAN 1/2 LSB ERROR, AT LESS THAN 100mV FROM ACTUAL THRESHOLD. THESE SWITCHING POINTS ARE GUARANTEED TO LIE BETWEEN 0.8V AND 2.0V OVER THE OPERATING TEMPERATURE RANGE (VLC = 0.0V).
TPC 7. Output Current vs. Output Voltage (Output Voltage Compliance)
TPC 8. Output Voltage Compliance vs. Temperature
TPC 9. Bit Transfer Characteristics
REV. B
-7-
DAC08
10 ALL BITS "HIGH" OR "LOW"
POWER SUPPLY CURRENT - mA POWER SUPPLY CURRENT - mA
10 BITS MAY BE "HIGH" OR "LOW" 8 7 6 5 4 3 2 1 0 2 4 6 8 10 12 14 16 18 20 0 -0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 V-, NEGATIVE POWER SUPPLY - V dc I- WITH IREF = 0.2mA I+ I- WITH IREF = 1mA I- WITH IREF = 2mA
POWER SUPPLY CURRENT - mA
10 ALL BITS "HIGH" OR "LOW" 9 8 7 6 5 4 3 2 1 0 -50 0 50 100 TEMPERATURE - C 150 V+ = +15V I+ V- = -15V IREF = 2.0mA I-
9 8 7 6 5 4 3 I+ 2 1 0 I-
9
V+, POSITIVE POWER SUPPLY - V dc
TPC 10. Power Supply Current vs. V+
TPC 11. Power Supply Current vs. V-
TPC 12. Power Supply Current vs. Temperature
BASIC CONNECTIONS
+VREF RREF IIN VIN RIN 15 IREF RREF R15 +VREF RREF 14 R15 (OPTIONAL) 15 HIGH INPUT IMPEDANCE +VREF MUST BE ABOVE PEAK POSITIVE SWING OF V IN PEAK NEGATIVE SWING OF IIN
IREF 14
MSB LSB B1 B2 B3 B4 B5 B6 B7 B8 IREF +VREF VREF (+) 14 5 6 7 8 9 10 11 12 IO 4 2 3 16 V- CC COMP IFR = +VREF RREF 255 0.1 F 256 0.1 F 13 V+ 1 IO FOR FIXED REFERENCE, TTL OPERATION, TYPICAL VALUES ARE: VREF = 10.000V RREF = 5.000k R15 = RREF CC = 0.01 F VLC = 0V (GROUND) VLC
RREF (R14) R15 VREF (-)
15
VIN
IO + IO = IFR FOR ALL LOGIC STATES
V-
V+
Figure 7. Accommodating Bipolar References
Figure 8. Basic Positive Reference Operation
LSB MSB B1 B2 B3 B4 B5 B6 B7 B8 IO IREF = 2.000mA 14 IO 2
EO 5.000k FULL RANGE HALF-SCALE +LSB HALF-SCALE HALF-SCALE -LSB ZERO-SCALE +LSB ZERO-SCALE
4 5.000k
B1 1 1 1 0 0 0
B2 1 0 0 1 0 0
B3 1 0 0 1 0 0
B4 1 0 0 1 0 0
B5 1 0 0 1 0 0
B6 1 0 0 1 0 0
B7 1 0 0 1 0 0
B8 1 1 0 1 1 0
IOmA 1.992 1.008 1.000 0.992 0.008 0.000
IOmA 0.000 0.984 0.992 1.000 1.984 1.992
EO -9.960 -5.040 -5.000 -4.960 -0.040 0.000
EO -0.000 -4.920 -4.960 -5.000 -9.920 -9.860
EO
Figure 9. Basic Unipolar Negative Operation
-8-
REV. B
DAC08
10.000V LSB MSB B1 B2 B3 B4 B5 B6 B7 B8 10.000k IO 14 IO 2 EO EO POS. FULL RANGE POS. FULL RANGE -LSB ZERO-SCALE +LSB ZERO-SCALE ZERO-SCALE -LSB NEG. FULL-SCALE +LSB NEG. FULL-SCALE B1 1 1 1 1 0 0 0 B2 1 1 0 0 1 0 0 B3 1 1 0 0 1 0 0 B4 1 1 0 0 1 0 0 B5 1 1 0 0 1 0 0 B6 1 1 0 0 1 0 0 B7 1 1 0 0 1 0 0 B8 EO 1 -9.920 0 -9.840 1 -0.080 0 0.000 1 +0.080 1 +9.920 0 +10.000 EO +10.000 +9.920 +0.160 +0.080 0.000 -9.840 -9.920 10.000k
IREF(+) = 2.000mA
4
Figure 10. Basic Bipolar Output Operation
LOW T.C. 4.5k 14 IREF(+) 2mA 39k 1V APPROX 5k 15 -VREF IFS R15 -VREF RREF RREF 14 4
VREF 10V
IO IO
10k POT
15
2
NOTE RREF SETS IFS; R15 IS FOR BIAS CURRENT CANCELLATION.
Figure 11. Recommended Full-Scale Adjustment Circuit
10k 5.0k 15V 2 10V 6 VO 5 5.0k V+ 4 *OR ADR01 +15V -15V -15V V- CC VLC IO 2 5.000k IO 4 OP711 MSB LSB B1 B2 B3 B4 B5 B6 B7 B8 +15V
Figure 12. Basic Negative Reference Operation
REF01*
B1 POS. FULL RANGE 1 1 EO ZERO-SCALE NEG. FULL-SCALE +1 LSB 0 NEG. FULL-SCALE 0
B2 1 0 0 0
B3 1 0 0 0
B4 1 0 0 0
B5 1 0 0 0
B6 1 0 0 0
B7 1 0 0 0
B8 EO 1 +4.960 0 0.000 1 -4.960 0 -5.000
Figure 13. Offset Binary Operation
RL 4 2 IO IO OP711 0 TO +IFR IFR = EO RL
4 2 IO IO RL OP711 0 TO -IFR EO RL
255 I 256 REF
255 IFR = I 256 REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4) TO GROUND.
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC), CONNECT NONINVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4) TO GROUND.
Figure 14. Positive Low Impedance Output Operation
Figure 15. Negative Low Impedance Output Operation
VTH = V LC 1.4V 15V CMOS VTH = 7.6V 15V TTL, DTL VTH = 1.4V 9.1k VLC VLC 1 6.2k 0.1 F 39k
CMOS, HTL, NMOS ECL V+
13k
20k
2N3904 "A" 3k 2N3904 TO PIN 1 VLC 6.2k "A"
2N3904 2N3904 3k 20k TO PIN 1 VLC R3 400 A
-5.2V
TEMPERATURE COMPENSATING V LC CIRCUITS
Figure 16. Interfacing with Various Logic Families
REV. B
-9-
DAC08
APPLICATION INFORMATION REFERENCE AMPLIFIER SETUP
The DAC08 is a multiplying D/A converter in which the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly zero to 4.0 mA. The full-scale output current is a linear function of the reference current and is given by: IFR = 255 x IREF , where IREF = I14 256
technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA) occurs in 120 ns when the equivalent impedance at Pin 14 is 200 and CC = 0. This yields a reference slew rate of 16 mA/s, which is relatively independent of RIN and VIN values.
LOGIC INPUTS
In positive reference applications, an external positive reference voltage forces current through R14 into the VREF(+) terminal (Pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to VREF(-) at Pin 15; reference current flows from ground through R14 into VREF(+) as in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at Pin 15. The voltage at Pin 14 is equal to and tracks the voltage at Pin 15 due to the high gain of the internal reference amplifier. R15 (nominally equal to R14) is used to cancel bias current errors; R15 may be eliminated with only a minor increase in error. Bipolar references may be accommodated by offsetting VREF or Pin 15. The negative common-mode range of the reference amplifier is given by: VCM- = V- plus (IREF x 1 k) plus 2.5 V. The positive common-mode range is V+ less 1.5 V. When a dc reference is used, a reference bypass capacitor is recommended. A 5.0 V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R14 should be split into two resistors with the junction bypassed to ground with a 0.1 F capacitor. For most applications the tight relationship between IREF and IFS will eliminate the need for trimming IREF. If required, full-scale trimming may be accomplished by adjusting the value of R14, or by using a potentiometer for R14. An improved method of full-scale trimming which eliminates potentiometer T.C. effects is shown in the recommended full-scale adjustment circuit. Using lower values of reference current reduces negative power supply current and increases reference amplifier negative common-mode range. The recommended range for operation with a dc reference current is 0.2 mA to 4.0 mA.
REFERENCE AMPLIFIER COMPENSATION FOR MULTIPLYING APPLICATIONS
The DAC08 design incorporates a unique logic input circuit that enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made possible by the large input swing capability, 2 A logic input current and completely adjustable logic threshold voltage. For V- = -15 V, the logic inputs may swing between -10 V and +18 V. This enables direct interface with 15 V CMOS logic, even when the DAC08 is powered from a 5 V supply. Minimum input logic swing and minimum logic threshold voltage are given by: V- plus (IREF x 1 k) plus 2.5 V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (Pin 1, VLC). The appropriate graph shows the relationship between VLC and VTH over the temperature range, with VTH nominally 1.4 above VLC. For TTL and DTL interface, simply ground pin 1. When interfacing ECL, an IREF = 1 mA is recommended. For interfacing other logic families, see preceding page. For general set-up of the logic control circuit, it should be noted that Pin 1 will source 100 A typical; external circuitry should be designed to accommodate this current. Fastest settling times are obtained when Pin 1 sees a low impedance. If Pin 1 is connected to a 1 k divider, for example, it should be bypassed to ground by a 0.01 F capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided where IO + IO = IFS. Current appears at the "true" (IO) output when a "1" (logic high) is applied to each logic input. As the binary count increases, the sink current at pin 4 increases proportionally, in the fashion of a "positive logic" D/A converter. When a "0" is applied to any input bit, that current is turned off at Pin 4 and turned on at Pin 2. A decreasing logic count increases IO as in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required, it must be connected to ground or to a point capable of sourcing IFS; do not leave an unused output pin open. Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other voltage source. Positive compliance is 36 V above V- and is independent of the positive supply. Negative compliance is given by V- plus (IREF x 1 k) plus 2.5 V. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers.
POWER SUPPLIES
AC reference applications will require the reference amplifier to be compensated using a capacitor from Pin 16 to V-. The value of this capacitor depends on the impedance presented to Pin 14: for R14 values of 1.0, 2.5 and 5.0 k, minimum values of CC are 15, 37 and 75 pF. Larger values of R14 require proportionately increased values of CC for proper phase margin, so the ratio of CC (pF) to R14 (k) = 15. For fastest response to a pulse, low values of R14 enabling small CC values should be used. If Pin 14 is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and slew rate. For R14 = 1 k and CC = 15 pF, the reference amplifier slews at 4 mA/s enabling a transition from IREF = 0 to IREF = 2 mA in 500 ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This
The DAC08 operates over a wide range of power supply voltages from a total supply of 9 V to 36 V. When operating at supplies of 5 V or less, IREF 1 mA is recommended. Low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode REV. B
-10-
DAC08
range, negative logic input range and negative logic threshold range; consult the various figures for guidance. For example, operation at -4.5 V with IREF = 2 mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower supplies is possible; however, at least 8 V total must be applied to ensure turn-on of the internal bias network. Symmetrical supplies are not required, as the DAC08 is quite insensitive to variations in supply voltage. Battery operation is feasible as no ground connection is required: however, an artificial ground may be used to ensure logic swings, etc., remain between acceptable limits. Power consumption may be calculated as follows: PD = (I+) (V+) + (I-) (V-) A useful feature of the DAC08 design is that supply current is constant and independent of input logic states; this is useful in cryptographic applications and further serves to reduce the size of the power supply bypass capacitors.
TEMPERATURE PERFORMANCE SETTLING TIME
The DAC08 is capable of extremely fast settling times, typically 85 ns at IREF = 2.0 mA. Judicious circuit design and careful board layout must be employed to obtain full performance potential during testing and application. The logic switch design enables propagation delays of only 35 ns for each of the 8 bits. Settling time to within 1/2 LSB of the LSB is therefore 35 ns, with each progressively larger bit taking successively longer. The MSB settles in 85 ns, thus determining the overall settling time of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns. The output capacitance of the DAC08 including the package is approximately 15 pF, therefore the output RC time constant dominates settling time if RL > 500 . Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for IREF values. The principal advantage of higher IREF values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant. Measurement of settling time requires the ability to accurately resolve 4 A, therefore a 1 k load is needed to provide adequate drive for most oscilloscopes. The settling time fixture shown in schematic labelled "Settling Time Measurement" uses a cascade design to permit driving a 1 k load with less than 5 pF of parasitic capacitance at the measurement node. At IREF values of less than 1.0 mA, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from 01111111 to 10000000 provides an accurate indicator of settling time. This code change does not require the normal 6.2 time constants to settle to within 0.2% of the final value, and thus settling times may be observed at lower values of IREF. DAC08 switching transients or "glitches" are very low and may be further reduced by small capacitive loads at the output at a minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference, and VLC terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1 F capacitors at the supply pins provide full transient protection.
The nonlinearity and monotonicity specifications of the DAC08 are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is low, typically 10 ppm/C, with zero-scale output current and drift essentially negligible compared to 1/2 LSB. The temperature coefficient of the reference resistor R14 should match and track that of the output resistor for minimum overall full-scale drift. Settling times of the DAC08 decrease approximately 10% at -55C; at +125C an increase of about 15% is typical. The reference amplifier must be compensated by using a capacitor from pin 16 to V-. For fixed reference operation, a 0.01 F capacitor is recommended. For variable reference applications, see "Reference Amplifier Compensation for Multiplying Applications" section.
MULTIPLYING OPERATION
The DAC08 provides excellent multiplying performance with an extremely linear relationship between IFS and IREF over a range of 4 A to 4 mA. Monotonic operation is maintained over a typical range of IREF from 100 A to 4.0 mA.
VL FOR TURN-ON, VL = 2.7V FOR TURN-OFF, VL = 0.7V 1k MINIMUM CAPACITANCE VCL 0.7V 1k 0.1 F Q1 VIN 1F 100k 4 2 13 3 16 0.01 F 0.1 F +15V -15V 0.1 F IOUT 2k 1F 50 F
+5V
Q2 VOUT 1X PROBE +0.4V 0V 0V -0.4V 0.1 F
RREF +VREF R15
15k
14 5 6 7 8 9 10 11 12
DAC08
15
-15V
Figure 17. Settling Time Measurement
REV. B
-11-
DAC08
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP (N-16)
0.840 (21.34) 0.745 (18.92)
16 1 9 8
16-Lead Cerdip (Q-16)
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204)
PIN 1
1 8
0.310 (7.87) 0.220 (5.59) 0.060 (1.52) 0.015 (0.38)
0.320 (8.13) 0.290 (7.37)
PIN 1 0.210 (5.33) MAX 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) SEATING 0.022 (0.558) 0.100 0.070 (1.77) PLANE (2.54) 0.045 (1.15) 0.014 (0.356) BSC
0.840 (21.34) MAX 0.200 (5.08) MAX
0.150 (3.81) 0.200 (5.08) MIN 0.125 (3.18) SEATING 0.023 (0.58) 0.100 0.070 (1.78) PLANE 0.014 (0.36) (2.54) 0.030 (0.76) BSC
15 0
0.015 (0.38) 0.008 (0.20)
16-Lead SO (R-16A)
0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 0.1497 (3.80)
16 1 9 8
20-Terminal Leadless Chip Carrier (E-20)
0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) TOP VIEW
45
0.2440 (6.20) 0.2284 (5.80)
0.358 (9.09) 0.342 (8.69) SQ
0.100 (2.54) 0.064 (1.63)
0.200 (5.08) BSC 0.100 (2.54) BSC
3 4 1
19 18
0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC
20
PIN 1
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
0.358 (9.09) MAX SQ
0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF
BOTTOM VIEW
14 13 8 9
0.0098 (0.25) 0.0040 (0.10)
8 0 0.0192 (0.49) SEATING 0.0099 (0.25) PLANE 0.0138 (0.35) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
0.088 (2.24) 0.054 (1.37)
0.055 (1.40) 0.045 (1.14)
45 TYP 0.150 (3.81) BSC
Revision History
Location Data Sheet changed from REV. A to REV. B. Page
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edit to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edits to Figures 14 and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Replacement of SO-16 with R-16A Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PRINTED IN U.S.A.
-12-
REV. B
C00268-0-2/02(B)

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